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C8051F93x/92x
5. Target Board
The C8051F930 Development Kit includes a target board with a C8051F930 device pre-installed for evaluation and
preliminary software development. Numerous input/output (I/O) connections are provided to facilitate prototyping
using the target board. Refer to Figure 8 for the locations of the various I/O connectors. Figure 10 on page 12
shows the factory default shorting block positions.
P1
P2
P3
J1
J2, J3, J4
J5
J6
J7
J8
J9
J10, J11
J12
J13
J14
J15
J16
J17
H1
H2
SW4
SW5
Expansion connector (96-pin)
Power connector (accepts input from 7 to 15 VDC unregulated power adapter)
USB connector (connects to PC for serial communication)
Enable/Disable VBAT Power LED
Port I/O headers (provide access to Port I/O pins)
Enable/Disable VDD/DC+ Power LED
Provides an easily accessible ground clip
Connects pin P0.7 (IREF0 Output) to resistor R14 and capacitor C19
Connects P0.2 and P0.3 to switches and P1.5 and P1.6 to LEDs
DEBUG connector for Debug Adapter interface
Selects the power supply source (Wall Power, AAA Battery, or Coin Cell)
Connects Port I/O to UART0 interface
Connects external VREF capacitor to the P0.0/VREF
Connects the PCB ground plane to P0.1/AGND
Connects negative potentiometer (R14) terminal to pin P1.4 or to GND
Connects the potentiometer (R14) wiper to P0.6/CNVSTR
Creates an open in the power supply path to allow supply current measurement
Analog I/O terminal block
Provides terminal block access to the input and output nodes of J17
Switches the device between One-Cell (0.9–1.8 V supply) or Two-Cell (1.8–3.6 V) mode
Turns power to the MCU on or off
P1.5 SW2
R15
J16
P1.4
J15
P1.6 P0.2 P0.3
SW3
USB POWER P3
GND
TOUCH SENSE SWITCH
P2.0
TOUCH SENSE SWITCH
P2.1
CP
2103
PORT2
J4
SILICON LABS
www.silabs.com
J8
U3
J12
J9
U1
+1VD
P1
F930
COIN_CELL
J11
J13
PORT1
J3
J7
AAA_BAT
WALL_PWR
SW1
J14 +3VD
VBAT
Pin 1
Pin 2
RESET
J6
VDD/DC+
PORT0
IMEASURE
J5
`
J2
J17
OFF
H2
VBAT
SW4
H1
ON
SW5
J1
P2
Pin 1
Figure 8. C8051F930 Target Board
10
Rev. 0.6
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